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Sitronix
1. INTRODUCTION
2
ST7571
4 Gray Scale Dot Matrix LCD Controller/Driver
ST7571 is a driver & controller LSI for 4-level gray scale graphic dot-matrix liquid crystal display systems. This chip is connected directly to a microprocessor, accepts Serial Peripheral Interface (SPI), I C or 8-bit parallel display data and stores in an on-chip display data RAM of 128 x 129 x 2 bits. It performs display data RAM write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
2. FEATURES
4-level (White, Light Gray, Dark Gray, Black) Gray Scale Display with PWM Method DDRAM Data [ 2n : 2n+1 ] 2n 0 0 1 1 Driver Output Circuits 128 segment outputs / 128+1 common outputs Various partial display Partial window moving & data scrolling Capacity: 128 x 129 x 2= 33,024 bits 8-bit parallel interface supports 6800-series or 8080-series MCU 4-line serial interface (4-Line SPI) 3-line serial interface (3-Line 8-bit SPI) I C serial interface
2
2n + 1 0 1 0 1
Gray Scale White Light gray Dark gray Black On-chip Low Power Analog Circuits On-chip oscillator circuit Build-in Voltage converter ( x8) Voltage regulator (temperature gradient: -0.13%/C) On-chip contrast control function (64 steps x 8) Voltage follower (LCD bias : 1/5 to 1/12) Digital Power (VDD1): 1.8V~3.3V (cover 1.7V~3.4V) Analog Power (VDD2, VDD3): 2.7V~3.3V (cover 2.6V~3.4V) Package Type Application for COG
(Accessible column address, n = 0, 1, 2, ......, 125, 126, 127)
Applicable Duty Ratios
On-chip Display Data RAM Microprocessor Interface
Operating Voltage Range
ST7571 ST7571i
6800 , 8080 , 4-Line , 3-Line interface (without I2C interface) I2C interface
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.
Ver 1.5a
1/76
2009/7/21
ST7571
3. PAD ARRANGEMENT (COG)
l l
Chip Size : 7956um X 780um Bump Pitch : I/O PAD : 80um COM PAD : 33um SEG PAD : 27um
l
Bump Size : I/O PAD : 65um X 63 um COM/SEG PAD : 14um X 128um
l l
Bump Height : 15um Chip Thickness : 300 um
Fig. 1 IC Pad Arrangement
Ver 1.5a 2/76 2009/7/21
ST7571
4. PAD CENTER COORDINATES
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Pin Name COM[126] COM[124] COM[122] COM[120] COM[118] COM[116] COM[114] COM[112] COM[110] COM[108] COM[106] COM[104] COM[102] COM[100] COM[98] COM[96] COM[94] COM[92] COM[90] COM[88] COM[86] COM[84] COM[82] COM[80] COM[78] COM[76] COM[74] COM[72] COM[70] COM[68] COM[66] COM[64] COM[62] COM[60] COM[58] X 3896.50 3863.50 3830.50 3797.50 3764.50 3731.50 3698.50 3665.50 3632.50 3599.50 3566.50 3533.50 3500.50 3467.50 3434.50 3401.50 3368.50 3335.50 3302.50 3269.50 3236.50 3203.50 3170.50 3137.50 3104.50 3071.50 3038.50 3005.50 2972.50 2939.50 2906.50 2873.50 2840.50 2807.50 2774.50 Y 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 PAD No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Pin Name COM[56] COM[54] COM[52] COM[50] COM[48] COM[46] COM[44] COM[42] COM[40] COM[38] COM[36] COM[34] COM[32] COM[30] COM[28] COM[26] COM[24] COM[22] COM[20] COM[18] COM[16] COM[14] COM[12] COM[10] COM[8] COM[6] COM[4] COM[2] COM[0] COMS1 SEG[0] SEG[1] SEG[2] SEG[3] SEG[4] X 2741.50 2708.50 2675.50 2642.50 2609.50 2576.50 2543.50 2510.50 2477.50 2444.50 2411.50 2378.50 2345.50 2312.50 2279.50 2246.50 2213.50 2180.50 2147.50 2114.50 2081.50 2048.50 2015.50 1982.50 1949.50 1916.50 1883.50 1850.50 1817.50 1784.50 1714.50 1687.50 1660.50 1633.50 1606.50 Y 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00
Ver 1.5a
3/76
2009/7/21
ST7571
PAD No. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Pin Name SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] X 1579.50 1552.50 1525.50 1498.50 1471.50 1444.50 1417.50 1390.50 1363.50 1336.50 1309.50 1282.50 1255.50 1228.50 1201.50 1174.50 1147.50 1120.50 1093.50 1066.50 1039.50 1012.50 985.50 958.50 931.50 904.50 877.50 850.50 823.50 796.50 769.50 742.50 715.50 688.50 661.50 Y 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 PAD No. 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Pin Name SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] X 634.50 607.50 580.50 553.50 526.50 499.50 472.50 445.50 418.50 391.50 364.50 337.50 310.50 283.50 256.50 229.50 202.50 175.50 148.50 121.50 94.50 67.50 40.50 13.50 -13.50 -40.50 -67.50 -94.50 -121.50 -148.50 -175.50 -202.50 -229.50 -256.50 -283.50 Y 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00
Ver 1.5a
4/76
2009/7/21
ST7571
PAD No. 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 Pin Name SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92] SEG[93] SEG[94] SEG[95] SEG[96] SEG[97] SEG[98] SEG[99] SEG[100] SEG[101] SEG[102] SEG[103] SEG[104] SEG[105] SEG[106] SEG[107] SEG[108] SEG[109] X -310.50 -337.50 -364.50 -391.50 -418.50 -445.50 -472.50 -499.50 -526.50 -553.50 -580.50 -607.50 -634.50 -661.50 -688.50 -715.50 -742.50 -769.50 -796.50 -823.50 -850.50 -877.50 -904.50 -931.50 -958.50 -985.50 -1012.50 -1039.50 -1066.50 -1093.50 -1120.50 -1147.50 -1174.50 -1201.50 -1228.50 Y 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 PAD No. 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 Pin Name SEG[110] SEG[111] SEG[112] SEG[113] SEG[114] SEG[115] SEG[116] SEG[117] SEG[118] SEG[119] SEG[120] SEG[121] SEG[122] SEG[123] SEG[124] SEG[125] SEG[126] SEG[127] COM[1] COM[3] COM[5] COM[7] COM[9] COM[11] COM[13] COM[15] COM[17] COM[19] COM[21] COM[23] COM[25] COM[27] COM[29] COM[31] COM[33] X -1255.50 -1282.50 -1309.50 -1336.50 -1363.50 -1390.50 -1417.50 -1444.50 -1471.50 -1498.50 -1525.50 -1552.50 -1579.50 -1606.50 -1633.50 -1660.50 -1687.50 -1714.50 -1784.50 -1817.50 -1850.50 -1883.50 -1916.50 -1949.50 -1982.50 -2015.50 -2048.50 -2081.50 -2114.50 -2147.50 -2180.50 -2213.50 -2246.50 -2279.50 -2312.50 Y 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00
Ver 1.5a
5/76
2009/7/21
ST7571
PAD No. 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 Pin Name COM[35] COM[37] COM[39] COM[41] COM[43] COM[45] COM[47] COM[49] COM[51] COM[53] COM[55] COM[57] COM[59] COM[61] COM[63] COM[65] COM[67] COM[69] COM[71] COM[73] COM[75] COM[77] COM[79] COM[81] COM[83] COM[85] COM[87] COM[89] COM[91] COM[93] COM[95] COM[97] COM[99] COM[101] COM[103] X -2345.50 -2378.50 -2411.50 -2444.50 -2477.50 -2510.50 -2543.50 -2576.50 -2609.50 -2642.50 -2675.50 -2708.50 -2741.50 -2774.50 -2807.50 -2840.50 -2873.50 -2906.50 -2939.50 -2972.50 -3005.50 -3038.50 -3071.50 -3104.50 -3137.50 -3170.50 -3203.50 -3236.50 -3269.50 -3302.50 -3335.50 -3368.50 -3401.50 -3434.50 -3467.50 Y 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 PAD No. 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 Pin Name COM[105] COM[107] COM[109] COM[111] COM[113] COM[115] COM[117] COM[119] COM[121] COM[123] COM[125] COM[127] COMS2 PS0 VSS1 PS1 VDD1 PS2 VSS1 CSB RST A0 RWR ERD D0 D1 D2 D3 D4 D5 D6 D7 RST CSB VDD1 X -3500.50 -3533.50 -3566.50 -3599.50 -3632.50 -3665.50 -3698.50 -3731.50 -3764.50 -3797.50 -3830.50 -3863.50 -3896.50 -3858.00 -3778.00 -3698.00 -3618.00 -3538.00 -3458.00 -3378.00 -3298.00 -3218.00 -3138.00 -3058.00 -2978.00 -2898.00 -2818.00 -2738.00 -2658.00 -2578.00 -2498.00 -2418.00 -2338.00 -2258.00 -2178.00 Y 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 283.00 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50
Ver 1.5a
6/76
2009/7/21
ST7571
PAD No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 Pin Name VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 VDD3 VDD3 VSS3 VSS3 VSS2 VSS2 VSS2 VSS2 VSS1 VSS1 VSS1 VSS1 VDD2 VDD2 VDD2 VDD2 VDD3 VDD3 MF2 MF1 MF0 DS0 DS1 VMO VMO VMO VSS2 V0I V0I X -2098.00 -2018.00 -1938.00 -1858.00 -1778.00 -1698.00 -1618.00 -1538.00 -1458.00 -1378.00 -1298.00 -1218.00 -1138.00 -1058.00 -978.00 -898.00 -818.00 -738.00 -658.00 -578.00 -498.00 -418.00 -338.00 -258.00 -178.00 -98.00 -18.00 62.00 142.00 222.00 302.00 382.00 462.00 542.00 622.00 Y -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 PAD No. 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 Pin Name V0I V0I V0S V0O V0O XV0O XV0O XV0S XV0I XV0I XV0I XV0I VDD1 VEXT OSC1 DCPS VSS1 CSEL VD1I VD1I VD1O VGO VGO VGS VGI VGI VGI VGI VPP VPP VPP VE DUMMY1 DUMMY2 DUMMY3 X 702.00 782.00 862.00 942.00 1022.00 1102.00 1182.00 1262.00 1385.00 1465.00 1545.00 1625.00 1705.00 1785.00 1865.00 1945.00 2025.00 2105.00 2185.00 2265.00 2345.00 2425.00 2505.00 2585.00 2665.00 2745.00 2825.00 2905.00 2985.00 3065.00 3145.00 3225.00 3341.00 3421.00 3501.00 Y -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50 -315.50
Ver 1.5a
7/76
2009/7/21
ST7571
PAD No. 351 352 353 354 Pin Name DUMMY4 DUMMY5 DUMMY6 DUMMY7 X 3581.00 3661.00 3741.00 3821.00 Y -315.50 -315.50 -315.50 -315.50
Note: 1. 2. CSEL=H. Unit: um.
Ver 1.5a
8/76
2009/7/21
DB0 DB1 DB2 DB3 DB4 DB5 DB7(SCL) ERD RWR A0 CSB RST PS0 PS1 PS2
Fig.2 Block diagram
DB6(SI)
5. BLOCK DIAGRAM
DS0 DS1 MF0 MF1 MF2
ST7571
Ver 1.5a
9/76
2009/7/21
ST7571
6. PIN DESCRIPTION
6.1 POWER SUPPLY
Power Supply Pin Description
Name VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 I/O Power Power Power Power Power Power Power supply for digital circuit. If VDD1 is the same level as VDD2, they can be connected together by FPC. Power supply for analog circuit (booster). Power supply for sensitive circuit (internal Vref regulator). VDD3 is the same level as VDD2, and they should be connected together by FPC. Ground for digital circuit. VSS1, VSS2 & VSS3 should be connected together by FPC. Ground for analog circuit (booster), it should be connected together by FPC. Ground for sensitive circuit (Vref regulator), it should be connected together by FPC. Description
6.2 LCD DRIVER SUPPLY
LCD Driver Supply Pin Description
Name V0O V0I V0S Power I/O Description V0 is the LCD driving voltage for common circuits at negative frame. V0O is the output of V0 regulator. V0S is the feedback of V0 regulator. V0I is the V0 input of common circuits. Be sure that: V0 VG > VM > VSS XV0 (under operation). V0O, V0I & V0S should be connected together by FPC. XV0O XV0I XV0S Power XV0 is the LCD driving voltage for common circuits at positive frame. XV0O is the output of XV0 regulator. XV0S is the feedback of XV0 regulator. XV0I is the XV0 input of common circuits. XV0O, XV0I & XV0S should be connected together by FPC. VG is the LCD driving voltage for segment circuits. VGO VGI VGS Power A storage capacitor on FPC or system for VG is required. VGO is the output of VG regulator. VGS is the feedback of VG regulator. VGI is the VG input of segment circuits. VGO, VGI & VGS should be connected together by FPC. Be aware that: 1.8V VG < VDD2. VMO is the output of VM, which is the LCD driving voltage for common circuits. A storage capacitor on FPC or system for VM is required. Be aware that: 0.7V < VM < VDD2. VMO Power When the internal power circuit is active, the VG and VM are generated according to the bias setting as shown below: LCD bias 1/N bias NOTE: N = 5 to 12 VG (2/N) x V0 VM (1/N) x V0
Ver 1.5a
10/76
2009/7/21
ST7571
6.3 SYSTEM CONTROL
System Control Pin Description
Name VEXT OSC1 DCPS I/O O I I Description Reserved for testing, must set with floating. Connect OSC1 to VDD1. This pin selects the supply voltage source of the digital circuit. If system VDD1 is 3.0V ~ 3.3V, set DCPS=L to select Internal Regulator as digital circuit power. If system VDD1 is 1.8V ~ 2.8V, set DCPS=H to select VDD1 as digital circuit power. Select COM output sequence. CSEL I Fix CSEL=H to enable "Interlace" mode (recommended). In interlace mode, COM2n (even number) is in the one side, COM(2n+1) (odd number) is in the opposite side. Short VD1I with VD1O externally by ITO or FPC. VD1I VD1O VE VPP MF[2:0] DS[1:0] Notes: 1. 2. 3. When system control pin set to "H", it should be connected to VDD1. When system control pin set to "L", it should be connected to VSS1. CSEL function is illustrated as the figure below:
COM127 COM125 COM126 COM124
O
VD1I is the power supply pin of the internal digital circuits. When DCPS=L, VD1O is the output of the internal digital power regulator. When DCPS=H, VD1O is provided by VDD1. When writing EEPROM, VE should be pull-high externally. When writing EEPROM, it needs external power supply voltage. Reserve for testing only, recommend setting to [ MF2,MF1,MF0 = 0,0,0 ]. Reserve for testing only, recommend setting to [ DS1,DS0 = 0,0 ].
I I I I
CSEL="H"
COM5 COM3 COM1 COM4 COM2 COM0
258
257
256
Gold Bump Face Up
196
195
194
65
64
63
62
2
1
Ver 1.5a
11/76
2009/7/21
ST7571
6.4 MICROPROCESSOR INTERFACE
Microprocessor Interface Pin Description
Name RST I/O I Reset input pin. When RST is "L", initialization is executed. PS[2:0] select the microprocessor interface: PS2 L L PS[2:0] I L L H PS1 L H L H L PS0 H H L L L Selected Interface Mode Parallel 8080 MPU Interface Parallel 6800 MPU Interface Serial 3-Line Interface Serial 4-Line Interface Serial I C Interface
2
Description
* NOTE: It is impossible to read data from the on-chip DDRAM. For detailed interface connection, please refer to Section 7.1 and Application Circuits. Chip select input pin. CSB I The interface is enabled only when CSB is "L" (except I C Interface). When CSB is non-active, DB[7:0] are high impedance. CSB is not used in I C interface; it is recommended to fix CSB at "H" by VDD1. Register select input pin. A0 I A0 = "H": DB0 to DB7 are display data. A0 = "L": DB0 to DB7 are control command. A0 is not used in serial 3-Line and I C interface; it is recommended to fix A0 at "H" by VDD1. Write execution control pin. PS2 RWR I L L PS1 H L PS0 H H MPU Type 6800-series 8080-series RWR R/W /WR Description Write control input pin. Keep this pin at "L" level. The data on DB[7:0] are latched at the rising edge of the /WR signal.
2 2 2
Read / Write execution control pin. PS2 ERD I L L PS1 H L PS0 H H MPU Type 6800-series 8080-series ERD E /RD Description The data on DB[7:0] are latched at the falling edge of the E signal. Keep this pin at "H" level.
Ver 1.5a
12/76
2009/7/21
ST7571
Name I/O When using parallel interface: I DB[7:0] are 8-bit data bus. DB[7:0] are connected to the 8-bit data bus of a standard microprocessor. When chip select is not active (CSB=H), DB[7:0] are high impedance. When using 3-Line/4-Line serial interface: DB7: serial input data (SID). I DB[7:0] DB6: serial input clock (SCLK). DB[5:0] are high impedance and must be fixed to "H". When chip select is not active (CSB=H), DB[7:0] are high impedance. When using I C interface: DB7: SCL, serial clock input. I/O DB[6:4]: SDA_IN, serial input data. DB[3:2]: SDA_OUT, output the acknowledge signal of the I C interface protocol. DB[6:2] must be connected together (SDA).
2 *1 2 2
Description
DB[1:0]: SA[1:0], I C slave address bits of ST7571. Must connect to VDD1 or VSS1. 1. By connecting SDA_OUT to SDA_IN externally, the SDA line becomes fully I C interface compatible. Separating acknowledge-output from serial data input is advantageous for chip-on-glass (COG) applications. In COG applications, the ITO resistance and the pull-up resistor will form a voltage divider, which affects acknowledge-signal level. Larger ITO resistance will raise the acknowledged-signal level and system cannot recognize this level as a valid logic "0" level. By separating SDA_IN from SDA_OUT, the IC can be used in a mode that ignores the acknowledge-bit. For applications which check acknowledge-bit, it is necessary to minimize the ITO resistance of the SDA_OUT trace to guarantee a valid low level. 2. After VDD1 is turned ON, any MPU interface pins cannot be left floating.
2
Ver 1.5a
13/76
2009/7/21
ST7571
6.5 LCD DRIVER OUTPUTS
LCD Driver Output Pin Description
Name I/O Description LCD segment driver outputs. The display data and frame signal control the output . Display Data SEG0 to SEG127 O H H L L Frame Positive Negative Positive Negative Segment Driver Output Voltage Normal Display VG VSS VSS VG VSS Reverse Display VSS VG VG VSS VSS
Display off / Power save mode
LCD common driver outputs. The internal scan signal and frame signal control the output voltage. Scan Signal COM0 to COM127 O H H L L Frame Positive Negative Positive Negative Common Driver Output Voltage XV0 V0 VM VM VSS
Display off / Power save mode COMS2 COMS1 O Common output for the icons.
The outputs at COMS1 and COMS2 are the same. When not used, these pins should be left open.
Recommend I/O Resistance
PIN Name PS[2:0], OCS1, VEXT, DCPS, MF[2:0], DS[1:0] VDD1, VDD2, VDD3, VSS1, VSS2, VSS3, VPP, VD1I, VD1O CSB , ERD, RWR, A0, DB[7:0], VE V0, VG, VM, XV0, VD1 RST Note: 1. 2. 3. 4. 5. 6. These Limitations include the bottleneck of ITO layout. Keep the ITO resistance of COM0 ~ COM127 be equal, and so it is of SEG0 ~ SEG127. If using I C interface mode, the resistance of SDA signal is recommended to be lower than 300 (if the system pull up resistor is 4.7K). If LCD panel size is larger than 1.5", the resistance limitations will be lower. To avoid the noise in different power system affect other power system, please separate different power source on ITO layout. Please refer to the ITO Layout Reference. The V0, XV0 and VG power circuits have output pins, input pins and a sensor input. To avoid the power noise affects the sensor of the power circuits. The trace should be separated by ITO and should be connected together by FPC.
2
ITO Resister <5K <100 <1K <500 <10K
Ver 1.5a
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VG I VG I VG I VSS 1 VG I VGS VGO VGO VSS1 VSS1 VSS1 VSS 2 VSS2 VSS2 VSS2 VSS3 VSS3 XV 0 I XV 0 I XV 0 I XV 0 I XV0S VDD3 VDD3 VDD 2 VDD2 VDD2 VDD2 V0O V0O VDD1 V0S VDD1 VDD1 V0 I V0 I V0 I V0 I XV0O XV0O
ITO Layout Reference
ST7571
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7. FUNCTIONAL DESCRIPTION
7.1 MICROPROCESSOR INTERFACE
Chip Select Input
CSB pin is used for chip selection. ST7571 can interface with an MPU when CSB is "L". When CSB is "H", the inputs of A0, ERD and RWR with any combination will be ignored and DB[7:0] are high impedance. In 3-Line and 4-Line serial interface, the internal shift register and serial counter are reset when CSB is "H".
Parallel / Serial Interface
ST7571 has types of interface for kinds of MPU. The MPU interface is selected by PS[2:0] pins as shown in Table 1. The read-function is not available. Table 1 Parallel / Serial Interface Mode PS2 PS1 PS0 Type CSB A0 ERD RWR L L /RD /WR H Parallel CSB A0 L H E R/W L L --L CSB ----Serial L H A0 H L L --------Note: The un-used pins are marked as "---" and should be fixed to "H" by VDD1. MPU Interface 8080-series parallel interface 6800-series parallel interface 3-Line SPI interface 4-Line SPI interface 2 I C Interface
Parallel Interface (PS2 = "L" & PS0 = "H")
The 8-bit data bus is used in parallel interface and the type of MPU is selected by PS1 as shown in Table 2. The type of data transfer is determined by signals at A0, ERD and RWR as shown in Table 3. Table 2 Microprocessor Selection for Parallel Interface PS1 L H Common A0 L H CSB CSB CSB A0 A0 A0 6800-series ERD (E) H H RWR (R/W) L L ERD RWR /RD /WR E R/W Table 3 Parallel Data Transfer 8080-series ERD (/RD) H H RWR (/WR) L L DB[7:0] DB[7:0] DB[7:0] MPU bus 8080-series 6800-series
Description Writes to internal register (instruction) Display data write
Serial Interface Selection
By setting PS[2:0], one of the Serial Interfaces can be selected. In 3-Line or 4-Line SPI mode, the internal 8-bit shift register and 3-bit counter are reset when IC is not active (CSB="H"). Serial mode 3-Line SPI 4-Line SPI I C SPI
2
PS[2:0] L, L, L L, H, L H, L, L
CSB CSB CSB ---
A0 --A0 ---
ERD -------
RWR ------DB[5:0]= ---
DB[7:0] DB7=SID, DB6=SCLK
2
Refer to I C Interface. DB7=SCL, DB[6:4]=SDA_IN, DB[3:2]=SDA_OUT, DB[1:0]=SA[1:0]
Note: The un-used pins are marked as "---" and should be fixed to "H" by VDD1.
Note: 1. 2. The pin setting to be "H" should connect to VDD1. The pin setting to be "L" should connect to VSS1.
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4-Line SPI Mode (PS0 = "L", PS1 = "H", PS2 = "L")
When IC is active (CSB="L"), serial data (SID) and serial clock (SCLK) inputs are enabled. When ST7571 is not active (CSB="H"), the internal 8-bit shift register and 3-bit counter are reset. The display data/command indication is controlled by the register selection pin (A0). The signals transferred on data bus will be display data when A0 is high and will be instruction when A0 is low. The read feature is not supported. Serial data on SID is latched at the rising edge of serial clock on SCLK. After the 8 serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column address pointer will be increased by one automatically after each byte of DDRAM access.
th
Fig. 3
4-line SPI Timing
3-Line SPI Mode (PS0 = "L", PS1 = "L", PS2= "L")
In 3-Line mode, default message from MCU is command. The Display Data Length command (2 bytes command) must be set before writing display data into Display Data RAM, after the display data is sent over, the next message is turned to be command. Signals on SID are latched at the rising edge of SCLK. After receiving 8-bit display data, the column address pointer of DDRAM will be increased by one automatically.
(1)
Set Page and Column Address. Command Set Page Address Set Column Address MSB Set Column Address LSB DB7 1 0 0 DB7 1 DB6 0 0 0 DB6 1 DB5 1 0 0 DB5 1 DB4 1 1 0 DB4 0 DB3 P3 0 X4 DB3 1 DB2 P2 X7 X3 DB2 0 DB1 P1 X6 X2 DB1 0 DB0 P0 X5 X1 DB0 0
(2)
Set Display Data Length (DDL) command and No. of Data Bytes. Command Set Display Data Length (DDL) Set No. of Data Bytes
Display Data Length (bytes)
(3)
This figure is an example for 104 Data bytes to be transferred. Fig. 4 3-Line SPI Timing (A0 is not used)
"Set Display Data Length" is used in 3-Line SPI mode only. It is 2-byte instruction: the first one informs the LCD driver and the second one sets the counter of input data (in bytes). After these two commands, the following messages will be data, till the data counter is cleared. If data is stopped during transmitting, it is not a valid data. A new data (8 bits) must write again. NOTE: If CSB is "H" before the end of a transmission, it stops this transfer and the next access should be re-initialized.
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I C Interface (PS0= "L", PS1= "L", PS2= "H")
The I C Interface is for bi-directional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock line (SCLK). Both lines must be connected with a pull-up resistor which drives SDA and SCLK to high when the bus is not busy. Data transfer can be initiated only when the bus is not busy. The I C interface of ST7571 supports write access and read of acknowledge-bit. The I C interface receives and executes the commands sent via the I C Interface. It also receives RAM data and sends it to the Display RAM. BIT TRANSFER One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse because changes of SDA line at this time will be interpreted as START or STOP. Bit transfer is illustrated in Fig 5.
2 2 2 2
2
Fig 5. START AND STOP CONDITIONS
Bit transfer
Both SDA and SCLK lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of SDA, while SCLK is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of SDA while SCLK is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Fig 6.
Fig 6.
Definition of START and STOP conditions
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SYSTEM CONFIGURATION The system configuration is illustrated in Fig 7 and some word-definitions are explained below: - Transmitter: the device which sends the data to the bus. - Receiver: the device which receives the data from the bus. - Master: the device which initiates a transfer, generates clock signals and terminates a transfer. - Slave: the device which is addressed by a master. - Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message. - Arbitration: the procedure to ensure that, if more than one master tries to control the bus simultaneously, only one is allowed to do so and the message is not corrupted. - Synchronization: procedure to synchronize the clock signals of two or more devices.
Fig 7. ACKNOWLEDGEMENT
System configuration
Each byte of eight bits is followed by an acknowledge-bit. The acknowledge-bit is a HIGH signal put on SDA by the transmitter during the time when the master generates an extra acknowledge-related clock pulse. A slave receiver which is addressed must generate an acknowledge-bit after the reception of each byte. A master receiver must also generate an acknowledge-bit after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge-clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end-of-data to the slave transmitter by not generating a acknowledge-bit on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I C Interface is illustrated in Fig 8.
2
Fig 8. Acknowledgement of I C Interface I C INTERFACE PROTOCOL ST7571 supports command/data write to addressed slaves on the bus. Before any data is transmitted on the I C Interface, the device, which should respond, is addressed first. Four 7-bit slave addresses (0111100, 0111101, 0111110 and 0111111) are reserved for ST7571. The least significant 2 bits of the slave address is set by connecting SA0 and SA1 to either logic 0 (VSS1) or logic 1 (VDD1). The I C Interface protocol is illustrated in Fig 9.
2 2 2
2
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The sequence is initiated with a START condition (S) from the I C Interface master, which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I C Interface transfer. After acknowledgement, one or more command words are followed and define the status of the addressed slaves. A command word consists of a control byte, which defines Co and A0, and a data byte. The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a cleared Co bit, only data byte(s) will follow. The state of the A0 bit defines whether the following data bytes are interpreted as commands or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte either a series of display data bytes or command data bytes may follow (depending on the A0 bit setting). If the A0 bit of the last control byte is set to logic 1, these data bytes (display data bytes) will be stored in the display RAM at the address specified by the internal data pointer. The data pointer is automatically updated and the data is directed to the intended ST7571 device. If the A0 bit of the last control byte is set to logic 0, these data bytes (command data byte) will be decoded and the setting of ST7571 will be changed according to the received commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the bus master issues a STOP condition (P). If no acknowledge is generated by the master after a byte, the driver stops transferring data to the master.
2 2
SA1 SA0
A0
R/W
Co
Co=1 A0
Co
Fig 9. Co 0 1
I C Interface protocol
2
Last control byte. Only a stream of data bytes is allowed to follow. This stream may only be terminated by a STOP or RE-START condition. Another control byte will follow the data byte.
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Co=0 A0
SA1 SA0 R/W
A0
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Data Transfer
ST7571 uses bus holder and internal data bus for data transfer by the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in Fig. 10 and Fig. 11.
Fig. 10
External Timing from MPU
Fig. 11
Internal Timing of IC
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7.2 DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 129-row by 128-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 129 rows are divided into 16 pages of 8 lines and the 17
th
page with a single line (DB0 only). Data is written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines. The LCD controller and MPU interface operate independently, data can be written into RAM at the same time when data is being displayed without flicker on LCD.
Page Address Circuit
It incorporates 4-bit Page Address register changed by only the "Set Page" instruction. Page Address 16 is a special RAM area for the icons and display data DB0 is only valid. The page address is set from 0 to 15, and Page 16 is for Icon page.
Line Address Circuit
This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 128-bit RAM data to the display data latch circuit. When icon is enabled by setting icon control register, display data of icons are not scrolled because the MPU can not access Line Address of icons.
Column Address Circuit
When set Column Address MSB / LSB instruction is issued, 7-bit (X[7:1]) are set and lowest bit (X0) is set to "0". The internal column address (X[7:0]) is increased by 1 automatically after each byte of data access (write data). After sequential access twice, the column address (X[7:1]) will point to the next column address. Please refer to Fig. 12.
Segment Control Circuit
This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF instructions without changing the data in the Display Data RAM. SEG 0 00H 00 1 01 1 02 1 SEG 1 01H 03 0 04 0 SEG 2 02H 05 1 06 0 SEG 3 03H 07 0 SEG 124 7CH F8 1 F9 1 SEG 125 7DH FA 1 FB 0 SEG 126 7EH FC 0 FD 1 SEG 127 7FH FE 0 FF 0
SEG Output Column Address X[7:1] Internal column address X[7:0] Display Data (MX=0) LCD panel display
... ... ... ... ...
Display data (MX=1) LCD panel display
0
0
0
1
1
0
1
1
... ...
0
0
0
1
1
0
1
1
Fig. 12 The Relationship between the Column Address and The Segment Outputs
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7.3 LCD DISPLAY CIRCUITS
Oscillator
This is on-chip Oscillator without external resistor. When the internal oscillator is used, this pin must connect to VDD1; when the external oscillator is used, this pin could be input pin. This oscillator signal is used in the voltage converter and display timing generation circuit.
Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, CL (internal), generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock and the display data latch circuit latches the 128-bit display data in synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (FR) which enables the LCD driver to make an AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. The frame signal or the line signal changes the M by setting internal instruction. Driving waveform and internal timing signal are shown in Fig. 13.
126 120 122 124 128 121 123 125 127 0
127 128 0
1
23
45
67
89
10 11
12
34
CL(Internal) FR(Internal) Frame
COM0
COM10
SEGn
Fig. 13 Frame AC Driving Waveform (Duty Ratio: 1/129)
Fig. 14
N-Line Inversion Driving Waveform (N=5,Duty Ratio=1/129)
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Partial Display on LCD
The ST7571 realizes the Partial Display function on LCD with low-duty driving for saving power consumption and showing the various display duty. To show the various display duty on LCD, LCD driving duty and bias are programmable via the instruction. And, built-in power supply circuits are controlled by the instruction for adjusting the LCD driving voltages. The partial display duty ratio could be set from 16 ~ 128. If the partial display region is out of the Max. Display range, it would be no operation.
-COM0 -COM1 -COM2 -COM3 -COM4 -COM5 -COM6 -COM7 -COM8 -COM9 -COM10 -COM11 -COM12 -COM13 -COM14 -COM15 -COM16 -COM17 -COM18 -COM19 -COM20 -COM21 -COM22 -COM23
Fig. 15
Reference Example for Partial Display
-COM0 -COM1 -COM2 -COM3 -COM4 -COM5 -COM6 -COM7 -COM8 -COM9 -COM10 -COM11 -COM12 -COM13 -COM14 -COM15 -COM16 -COM17 -COM18 -COM19 -COM20 -COM21 -COM22 -COM23
Fig. 16 Partial Display (Partial Display Duty=16, initial COM0=0)
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-COM0 -COM1 -COM2 -COM3 -COM4 -COM5 -COM6 -COM7 -COM8 -COM9 -COM10 -COM11 -COM12 -COM13 -COM14 -COM15 -COM16 -COM17 -COM18 -COM19 -COM20 -COM21 -COM22 -COM23
Fig. 17 Moving Display (Partial Display Duty=16, initial COM0=8)
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7.4 POWER SUPPLY CIRCUITS
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction.
Voltage Regulator Circuits
The internal Voltage Regulator circuit provides the liquid crystal operating voltage (V0) by adjusting resistors (SRR and EV). The parameter "SRR" can be set by "Select Regulator Register". The parameter "EV" can be set by "Set Electronic Volume Register", and the range of EV is 0~63. (63- EV) V0 = SRR x (1 - ------------) x 2.1 210 Table 5 Internal Regulator Ratio depending on 3-bit Data (R2 R1 R0) 3-bit data settings (R2 R1 R0) 000 SRR (Select Regulator Ratio) 2.3 001 3.0 010 3.7 011 4.4 100 5.1 101 5.8 110 6.5 111 7.2
Fig. 18 shows V0 voltage measured by adjusting regulator register ratio and 6-bit electronic registers for each temperature coefficient at Ta = 25C. The recommended range of EV setting is level 16 ~ 47.
16 14 12 10 8 6 4 2 0
0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
000 001 010 011 100 101 110 111
Fig. 18 Electronic Volume Level (25C)
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Voltage Follower Circuits
V0 is resistively divided into two voltage levels (VG, VM), and those output impedance are converted by the Voltage Follower for increasing drive capability. Table 6 shows the relationship between VG to VM level and each duty ratio. Table 6 The Relationship between V1 to V4 Level and Each Duty Ratio LCD Bias 1/N VG 2/N x V0 VM 1/N x V0 Remarks N = 5 to 12
Booster Efficiency
The Booster Efficiency Command could be used to choose the best Booster performance. Booster Efficiency (Level1~4) can easily set the best Booster performance with suitable current consumption. If the Booster Efficiency is set to a higher level (level2 is higher than level1), the Boost Efficiency is better than lower level, and it just needs few more power consumption current. When the LCD Panel loading is heavier, the performance of Booster Efficiency will be lower. We could select higher BE level to improve the efficiency with just few more current increased.
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7.5 RESET CIRCUITS
Setting RST to "L" can initialize internal function. RST pin is connected to the reset pin of MPU and initialization by RST pin is essential before operating. Please note the hardware reset is not same as the software reset. When RST becomes "L", the hardware reset procedure will start. When RESET instruction is executed, the software reset procedure will start. The procedure is listed below: Procedure Clear Serial Counter and Shift Register (if using Serial Interface) Page Address, P[3:0]=0 (Page 0) Column Address, X[7:0]=00h (Column 0) Display ON/OFF, D=0 (Display OFF) Reverse Display, REV=0 (Normal) Entire Display ON, EON=0 (Normal) Icon Control, ION=0 (OFF) Start Line, S[6:0]=0 (1 line of DDRAM) COM0, C[6:0]=0 (COM0 Pin) Display Duty, L[7:0]=0 (1/129) N-Line, N[4:0]=0 (N-Line OFF) Power Control, VC=0, VR=0, VF=0 (Internal Power OFF) Booster Efficiency, BE[1:0]=0,1 (Level 2) Regulator Resistor, R[2:0]=0,0,0 Contrast Control, EV[5:0]=20h LCD Bias, BS[2:0]=1,1,1 (1/12 bias) Frame Rate, FR[3:0]=0,0,0,0 (77Hz) COM Scan Direction, MY=0 (Normal) SEG Scan Direction, MX=0 (Normal) Oscillator Circuit: OFF Power-Save Mode, P=0 (Release) Display Data Length, DL[7:0]=00h (for 3-Line serial interface only)
st
Hardware Reset V V V V V V V V V V V V V V V V V V V V V V
Software Reset V V V X X X X V X X X X X V V X X X X X X V
After power-on, RAM data are undefined and the display status is "Display OFF". It's recommended to initialize the whole DDRAM (ex: fill all 00h or write a display pattern) before turning the Display ON (including the ICON RAM as well). Besides, the system power is not stable at the time that the power is just turned ON. After the system power is stable, a hardware reset is required to initialize internal registers.
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8. INSTRUCTIONS
Instruction A0 R/W 0 Set Mode 0 Write Display Data 1 0 0 FR3 FR2 FR1 FR0 BE1 BE0 -0 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 0 DB1 0 DB0 0 Description 2-byte instruction FR[3:0]: Set frame frequency BE[1:0]: Set booster efficiency Write data into DDRAM ION=0: Disable Icon function Set Icon 0 0 1 0 1 0 0 0 1 ION ION=1: Enable Icon function and set Page Address = 16 Set Page Address Set Column Address (MSB) Set Column Address (LSB) Display ON/OFF 0 0 0 0 0 Set Display Start Line 0 0 Set COM0 0 0 Set Display Duty 0 0 Set N-line Inversion 0 Release N-line Inversion Reverse Display 0 0 0 0 0 -1 1 -1 0 -1 1 N4 0 0 N3 0 0 N2 1 1 N1 0 1 N0 0 REV REV=1: Reverse display EON=0: Normal display Entire Display ON 0 0 1 0 1 0 0 1 0 EON EON=1: Entire display ON 9.1.14 inversion counter Exit N-line inversion mode REV=0: Normal display 9.1.13 9.1.12 0 0 L7 0 L6 1 L5 0 L4 0 L3 1 L2 1 L1 -L0 -duty 2-byte instruction. Set N-line 9.1.11 0 0 -0 C6 1 C5 0 C4 0 C3 1 C2 0 C1 -C0 -0 0 -0 S6 1 S5 0 S4 0 S3 0 S2 1 S1 -S0 -0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 1 1 0 0 0 P3 0 X4 1 0 P2 X7 X3 1 0 P1 X6 X2 1 -P0 X5 X1 D D=1: Display ON -2-byte instruction. Specify Line Address for the 1st display line of DDRAM (vertical scrolling). 2-byte instruction. Specify a COM pin to be COM0 (moving partial display window). 2-byte instruction. Set display 9.1.10 9.1.9 9.1.8 Set Page Address Set MSB of Column Address Set LSB of Column Address D=0: Display OFF 9.1.7 9.1.4 9.1.5 9.1.6 9.1.3 9.1.2 9.1.1 Section
Write data
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Instruction Power Control Select Regulator Register A0 R/W 0 0 0 Set Contrast 0 Select LCD bias 0 0 0 -0 -1 EV5 0 EV4 1 EV3 0 EV2 B2 EV1 B1 EV0 B0 internal Regulator's reference Select LCD bias Set COM scan direction: Set COM Scan Direction 0 0 1 1 0 0 MY ---MY=0: Normal direction MY=1: Reverse direction Set SEG scan direction: Set SEG Scan Direction 0 0 1 0 1 0 0 0 0 MX MX=0: Normal direction MX=1: Reverse direction Oscillator ON Set Power-Save Mode Release Power-Save Mode RESET Set Display Data Length -NOP Reserved Reserved Reserved Extension Command Set1 Extension Command Set2 Extension Command Set3 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 DL7 1 1 1 1 1 1 0 DL6 1 1 1 1 1 1 1 DL5 1 1 1 1 1 0 1 DL4 0 0 0 1 1 1 1 DL3 0 0 1 -1 0 1 DL2 0 0 1 -1 0 0 DL1 1 0 1 -0 0 1 DL0 1 0 0 -TE1 TE2 TE3 counter in 3-Line SPI only No operation Do NOT use Do NOT use Reserved for testing TE1=1: Enter extension Mode1 TE2=1: Enter extension Mode2 TE3=1: Enter extension Mode3 9.1.26 ---9.1.27 9.1.28 9.1.29 0 0 0 0 -0 0 0 0 -1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 P P=1: Enable Power-Save mode 1 0 0 Exit Power-Save mode Software reset 2-byte instruction. Set the data 9.1.25 9.1.23 9.1.24 Turn ON internal Oscillator P=0: Normal mode 9.1.22 9.1.21 9.1.20 9.1.19 9.1.18 0 0 0 DB7 0 0 1 DB6 0 0 0 DB5 1 1 0 DB4 0 0 0 DB3 1 0 0 DB2 VC R2 0 DB1 VR R1 0 DB0 VF R0 resistor 1 2-byte instruction. Select EV for 9.1.17 Description Set internal power ON/OFF Select internal Regulator 9.1.16 Section 9.1.15
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Instruction A0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description EXTENSION COMMAND SET 1 Increase Vop offset Decrease Vop offset Return normal mode 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 Increase vop offset by 1step Decrease vop offset by 1 step Return normal mode
EXTENSION COMMAND SET 2 Disable autoread Enter EEPROM mode Enable read mode Set read pulse Exit EEPROM mode Enable erase mode Set erase pulse Enable write mode Set write pulse Return normal mode 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 Disable autoread Enter EEPROM mode Enable read mode Set read pulse width Exit EEPROM mode Enable erase mode Set erase pulse width Enable write mode Set write pulse width Return normal mode
EXTENSION COMMAND SET 3 Select Black/White or Gray mode Set Color Mode 0 0 0 0 0 1 0 0 0 B/G B/G=1: Black/White mode; B/G=0: Gray mode (default) Return normal mode 0 0 0 0 0 0 0 0 0 0 Return normal mode
Note: Do NOT use non-specified instructions in any extension command mode.
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9. INSTRUCTION DESCRIPTION
9.1.1 Set Mode
This 2-byte instruction specifies frame frequency (FR[3:0]) and booster efficiency (BE[1:0]) The 1 Instruction A0 0 The 2
nd st
R/W 0 Instruction R/W 0
DB7 0
DB6 0
DB5 1
DB4 1
DB3 1
DB2 0
DB1 0
DB0 0
A0 0
DB7 FR3
DB6 FR2
DB5 FR1
DB4 FR0
DB3 BE1
DB2 BE0
DB1 x'
DB0 0
Frame Frequency FR[3:0] specifies the frame frequency: FR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Booster Efficiency The efficiency of internal Booster is configurable by BE[1:0]. The optimized setting is Level-3. BE1 0 0 1 1 BE0 0 1 0 1 Booster Efficiency Level 1 Booster Efficiency Level 2 Booster Efficiency Level 3 Booster Efficiency Level 4 Description FR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Frame Frequency 77 Hz 10% 51 Hz 20% 55 Hz 20% 58 Hz 20% 63 Hz 20% 67 Hz 20% 68 Hz 20% 70 Hz 20% 73 Hz 20% 75 Hz 20% 80 Hz 20% 85 Hz 20% 91 Hz 20% 102 Hz 20% 113 Hz 20% 123 Hz 20%
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9.1.2 Write Display Data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written. A0 1 R/W 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Write data
Write Data Flow
Set Page Address (0~15)
Set Column Address
Write Data
Column = Column +1 (Auto Increment)
Write more Data?
No
Yes
Write Data End
Fig. 20 Sequence for Writing Display Data
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9.1.3 Set Icon
This instruction makes Icon function enable or disable. After reset, the Icon function is disabled (ION=0). When ION="1", Icon display is enabled and the page address is set to "16" for updating icon data (it is impossible to set page address to "16" by Set Page Address instruction). Therefore, when writing data for icons, "Set Icon" instruction is necessary before writing icon data. It set the page address to "16" before writing icon data. When "ION" is "0", Icon display function is not available. A0 0 R/W 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 ION
ION 0 1 Disable Icon function
Description Enable Icon display and set Page Address to "16".
Fig. 20 Sequence for Writing Display Data
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9.1.4 Set Page Address
This instruction sets the Page Address of display data RAM from the microprocessor into the page address register. Any RAM data bit can be accessed when its Page Address and column address are specified. Along with the column address, the Page Address defines the address of the display RAM to write display data. Changing the Page Address doesn't affect the display status. Set Page Address instruction can not be used to set the page address to "16". Use ICON control register ON/OFF instruction to set the page address to "16". A0 0 R/W 0 DB7 1 DB6 0 DB5 1 DB4 1 DB3 P3 DB2 P2 DB1 P1 DB0 P0
P3 0 0 : 1 1
P2 0 0 : 1 1
P1 0 0 : 1 1
P0 0 1 : 0 1
Page 0 1 : 14 15
9.1.5 & 9.1.6 Set Column Address
These instructions set the specified column address of DDRAM into the internal Column Address register. The internal Column Address register points to the address of DDRAM for accessing display data. The Column Addresses register is automatically increased by 1 when the microprocessor accesses the display data in DDRAM. Set Column Address (MSB) A0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 0 DB2 X7 DB1 X6 DB0 X5
Set Column Address (LSB) A0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 X4 DB2 X3 DB1 X2 DB0 X1
X7 0 0 : 1 1
X6 0 0 : 1 1
X5 0 0 : 1 1
X4 0 0 : 1 1
X3 0 0 : 1 1
X2 0 0 : 1 1
X1 0 1 : 0 1
Column Address 0 1 : 126 127
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9.1.7 Display ON / OFF
This instruction turns the display ON or OFF. It has priority over Entire Display ON/OFF and Reverse Display ON/OFF. A0 0 R/W 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 DON
DON = 1: display ON DON = 0: display OFF
9.1.8 Set Display Start Line
This 2-byte instruction sets the line address of DDRAM to determine the first display line. The display data of the selected line will be displayed at the top of row (COM0) on the LCD panel. The 1 Instruction A0 0 The 2
nd st
R/W 0 Instruction R/W 0
DB7 0
DB6 1
DB5 0
DB4 0
DB3 0
DB2 0
DB1 x
DB0 x
A0 0
DB7 x
DB6 S6
DB5 S5
DB4 S4
DB3 S3
DB2 S2
DB1 S1
DB0 S0
S6 0 0 0 0 : 1 1 1 1
S5 0 0 0 0 : 1 1 1 1
S4 0 0 0 0 : 1 1 1 1
S3 0 0 0 0 : 1 1 1 1
S2 0 0 0 0 : 1 1 1 1
S1 0 0 1 1 : 0 0 1 1
S0 0 1 0 1 : 0 1 0 1
Line address 0 1 2 3 : 124 125 126 127
Fig.
21
Sequence for Setting Display Start Line
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9.1.9 Set COM0
This 2-byte instruction set the initial row (COM) of the LCD panel. By using this instruction, it is possible to realize the window moving without the change of display data. The 1 Instruction A0 0 The 2
nd st
R/W 0 Instruction R/W 0
DB7 0
DB6 1
DB5 0
DB4 0
DB3 0
DB2 1
DB1 x
DB0 x
A0 0
DB7 x
DB6 C6
DB5 C5
DB4 C4
DB3 C3
DB2 C2
DB1 C1
DB0 C0
C6 0 0 0 0 : 1 1 1 1
C5 0 0 0 0 : 1 1 1 1
C4 0 0 0 0 : 1 1 1 1
C3 0 0 0 0 : 1 1 1 1
C2 0 0 0 0 : 1 1 1 1
C1 0 0 1 1 : 0 0 1 1
C0 0 1 0 1 : 0 1 0 1
Initial COM0 COM0 COM1 COM2 COM3 : COM124 COM125 COM126 COM127
Fig. 22 Sequence for Setting COM0
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9.1.10 Set Display Duty
This 2-byte instruction sets the display duty within the range of 1/(16+1) to 1/(128+1) to realize partial display. The 1 Instruction A0 0 The 2
nd st
R/W 0 Instruction R/W 0
DB7 0
DB6 1
DB5 0
DB4 0
DB3 1
DB2 0
DB1 x
DB0 x
A0 0
DB7 L7
DB6 L6
DB5 L5
DB4 L4
DB3 L3
DB2 L2
DB1 L1
DB0 L0
L7 0 : 0 0 0 : 0 : 0 1 1 : 1
L6 0 : 0 0 0 : 1 : 1 0 0 : 1
L5 0 : 0 0 0 : 1 : 1 0 0 : 1
L4 0 : 0 1 1 : 0 : 1 0 0 : 1
L3 0 : 1 0 0 : 0 : 1 0 0 : 1
L2 0 : 1 0 0 : 1 : 1 0 0 : 1
L1 0 : 1 0 0 : 0 : 1 0 0 : 1
L0 0 : 1 0 1 : 0 : 1 0 1 : 1
Selected Partial Duty Ratio No Operation
1/(16+1) 1/(17+1) : 1/(100+1) : 1/(127+1) 1/(128+1) No Operation
NOTE: The duty includes the duty for ICON.
Fig. 23
Sequence for Setting Display Duty
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9.1.11 Set N-line Inversion (recommended 12-line inversion for full duty, 1/129 duty)
This 2-byte instruction sets the inverted line number within range of 3 to 33 to improve the display quality by controlling the phase of the internal Frame signal. The DC bias maybe occurred if the N-line is not set well. Be sure to confirm this factor after choosing a value of N. The 1 Instruction A0 0 The 2
nd st
R/W 0 Instruction R/W 0
DB7 0
DB6 1
DB5 0
DB4 0
DB3 1
DB2 1
DB1 x
DB0 x
A0 0
DB7 x
DB6 x
DB5 x
DB4 N4
DB3 N3
DB2 N2
DB1 N1
DB0 N0
N4 0 0 0 0 : 0
N3 0 0 0 0 : 1
N2 0 0 0 0 : 0
N1 0 0 1 1 : 1
N0 0 1 0 1 : 0
Selected n-line inversion 0-line inversion (frame inversion) 3-line inversion 4-line inversion 5-line inversion : 12-line inversion : (Recommend)
1 1 1
1 1 1
1 1 1
0 1 1
1 0 1
31-line inversion 32-line inversion 33-line inversion
Fig. 24 Sequence for N-line Inversion
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9.1.12 Release N-line Inversion
This instruction makes the inversion mode back to the frame inversion from the N-line inversion. A0 0 R/W 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 1 DB1 0 DB0 0
9.1.13 Reverse Display
This instruction reverses the display status on LCD panel without rewriting new contents into DDRAM. A0 0 R/W 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 1 DB0 REV
REV 0 (normal) 1 (reverse)
Pixel Data in DDRAM "00" (White) White Black "01" (Light Gray) Light Gray Dark gray "10" (Dark Gray) Dark Gray Light gray "11" (Black) Black White
9.1.14 Entire Display ON
This instruction forces the whole LCD pixels to be turned ON, regardless of the contents in DDRAM. The contents in DDRAM are not changed. This instruction has priority over the Reverse Display instruction. A0 0 R/W 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 0 DB0 EON
EON 0 (normal) 1 (entire ON)
Pixel Data in DDRAM "00" (White) White Black "01" (Light Gray) Light Gray Black "10" (Dark Gray) Dark Gray Black "11" (Black) Black Black
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9.1.15 Power Control
This instruction selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. A0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 1 DB2 VC DB1 VR DB0 VF
VC 0 1
VR
VF
Internal Power Supply Circuits Internal voltage converter circuit
Status OFF ON OFF ON OFF ON
0 1 0 1
Internal voltage regulator circuit Internal voltage follower circuit
9.1.16 Select Regulator Resister
This instruction selects resistance ratio of the internal regulator resistors. Refer to the voltage regulator circuits in power supply circuit section. A0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 0 DB2 R2 DB1 R1 DB0 R0
R2 0 0 0 0 1 1 1 1
R1 0 0 1 1 0 0 1 1
R0 0 1 0 1 0 1 0 1
1+ (Rb / Ra) 2.3 3.0 3.7 4.4 5.1 5.8 6.5 7.2
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9.1.17 Set Electronic Volume Register
This is 2-byte Instruction. The 1 instruction enters Reference Voltage mode, and the 2 reference voltage register. After 2
st nd st nd
one updates the contents of the
instruction, Reference Voltage mode is released. DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
The 1 Instruction: Set Reference Voltage Select Mode A0 0 The 2
nd
R/W 0
DB7 1
Instruction: Set Reference Voltage Register R/W 0 DB7 x DB6 x DB5 EV5 DB4 EV4 DB3 EV3 DB2 EV2 DB1 EV1 DB0 EV0
A0 0
EV5 0 0 : : 1 1
EV4 0 0 : : 1 1
EV3 0 0 : : 1 1
EV2 0 0 : : 1 1
EV1 0 0 : : 1 1
EV0 0 1 : : 0 1
EV Value 0 1 : : 62 63
9.1.18 Select LCD Bias
This instruction selects LCD bias ratio for the internal voltage follower to drive the LCD. A0 0 R/W 0 DB7 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 B2 DB1 B1 DB0 B0
B2 0 0 0 0 1 1 1 1
B1 0 0 1 1 0 0 1 1
B0 0 1 0 1 0 1 0 1
LCD bias 1/5 1/6 1/7 1/8 1/9 1/10 1/11 1/12
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9.1.19 Set COM Scan Direction
This instruction selects the COM output scanning direction and determines the LCD driver output status. A0 0 R/W 0 DB7 1 DB6 1 DB5 0 DB4 0 DB3 SHL DB2 x DB1 x DB0 x
SHL = 0: normal direction (COM0 ~ COM127) SHL = 1: reverse direction (COM127 ~ COM0)
9.1.20 Set SEG Scan Direction
This instruction changes the relationship between the DDRAM column address and the segment driver. The SEG scan direction can be reversed by this instruction. This feature makes IC layout more flexible for LCD module assembly. A0 0 R/W 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 ADC
ADC = 0: normal direction (SEG0 ~ SEG127) ADC = 1: reverse direction (SEG127 ~ SEG0)
9.1.21 Oscillator ON Start
This instruction enables the built-in oscillator circuit. A0 0 R/W 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 0 DB1 1 DB0 1
9.1.22 & 9.1.23 Power Save
ST7571 enters Power-Save mode and reduces the power consumption to the static power consumption. It returns to the normal operation mode by the Release Power Save Mode instruction. Set Power Save Mode A0 0 R/W 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 0 DB1 0 DB0 P
P = 0: normal mode P = 1: power-save mode (sleep mode)
Fig. 25 Internal Procedure of Power Save Release Power Save Mode A0 0 R/W 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
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9.1.24 RESET
This is software reset. It resets internal registers. The software reset is different with a hardware reset. This instruction cannot initialize the LCD power supply, which is initialized by a hardware reset (refer to section 7.5 RESET CIRCUITS). A0 0 R/W 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0
9.1.25 Set Display Data Length (only for 8-bit 3-Line SPI Mode)
This 2-byte instruction is used in 3-Line SPI mode only. In 3-Line SPI mode, A0 is not used and "Set Display Data Length" instruction is used to indicate the number of display data bytes which are going to be transmitted. The 1 byte sets the mode, and the 2
st nd st
byte sets the data bytes, which will be written, into internal counter. The next byte after the display data
string is handled as instruction. The 3-Line SPI mode supports write-access only. The 1 Instruction: Set Display Data Length Command (Only Write Mode) A0 x The 2
nd
R/W x
DB7 1
DB6 1
DB5 1
DB4 0
DB3 1
DB2 0
DB1 0
DB0 0
Instruction: Set Display Data Length Counter R/W x DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
A0 x
D7 0 0 0 : 1 1 1
D6 0 0 0 : 1 1 1
D5 0 0 0 : 1 1 1
D4 0 0 0 : 1 1 1
D3 0 0 0 : 1 1 1
D2 0 0 0 : 1 1 1
D1 0 0 1 : 0 1 1
D0 0 1 0 : 1 0 1
Display Data Length 1 2 3 : 254 255 256
9.1.26 NOP
No operation A0 0 R/W 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 1
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9.1.27 Extension Command Set1
This instruction enables the extension command set-1. A0 0 R/W 0 DB7 1 DB6 1 DB5 1 DB4 1 DB3 1 DB2 1 DB1 0 DB0 1
9.1.28 Extension Command Set2
This instruction enables the extension command set-2. A0 0 R/W 0 DB7 1 DB6 1 DB5 0 DB4 1 DB3 0 DB2 0 DB1 0 DB0 1
9.1.29 Extension Command Set3
This instruction enables the extension command set-3. A0 0 R/W 0 DB7 0 DB6 1 DB5 1 DB4 1 DB3 1 DB2 0 DB1 1 DB0 1
Extension Command Set 1
After entering the extension mode-1, the extension command set-1 is enabled. These commands are valid only in this mode. Always remember to return back to normal mode for correct operation.
Increase Vop Offset
This instruction increases the Vop offset (Vof[4:0]) by 1. A0 0 R/W 0 DB7 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 0 DB1 0 DB0 1
Decrease Vop Offset
This instruction decreases the Vop offset (Vof[4:0]) by 1. A0 0 Fine Tune Vop The "Increase Vop Offset" and "Decrease Vop Offset" instructions fine tune the voltage of Vop. The relation is shown below: R/W 0 DB7 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 0 DB1 1 DB0 0
Note: 1. The range is limited. If continuously setting "Increase Vop Offset", Vof[4:0] will increase. When Vof[4:0] is 0x0F and followed by a "Increase Vop Offset" command, Vof[4:0] will become 0x10. As the result, Vop changes from +15 step to -16 step. Software programmer should add a software protection to prevent that an operator maybe presses the "Increase Button" too many times accidentally. 2. EV"[5:0] = EV[5:0] + Vof[4:0] and EV"[5:0] 0x3F. If EV[5:0] + Vof[4:0] > 0x3F, EV"[5:0] will truncate the invalid bit.
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Return to Normal Mode
This instruction returns IC into normal mode and the general commands are available. A0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
Extension Command Set 2
After entering the extension mode-2, the extension command set-2 is enabled. These commands are valid only in this mode. Always remember to return back to normal mode for correct operation.
Disable auto-Read
This instruction disables the EEPROM auto-read function and lets the related registers can be set manually. A0 0 R/W 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 0 DB1 1 DB0 0
Enter EEPROM Mode
This instruction enters EEPROM mode. A0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 0 DB2 0 DB1 1 DB0 1
Enable Read Mode
This instruction enables the manually-read function. A0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
Set Read Pulse
This instruction generates one read cycle to read the contents in EEPROM. A0 0 R/W 0 DB7 0 DB6 1 DB5 1 DB4 1 DB3 0 DB2 0 DB1 0 DB0 1
Exit EEPROM Mode
This instruction exits EEPROM mode. A0 0 R/W 0 DB7 1 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 1
Enable ERASE Mode
This instruction enables manually-erase function. A0 0 R/W 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 1 DB2 0 DB1 1 DB0 0
Set ERASE Pulse
This instruction generates one erase cycle to erase the contents in EEPROM. A0 0 R/W 0 DB7 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 1 DB1 0 DB0 1
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Enable Write Mode
This instruction enables manually-write function. A0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 0 DB2 1 DB1 0 DB0 1
Set Write Pulse
This instruction generates one write cycle to write parameters into EEPROM. A0 0 R/W 0 DB7 0 DB6 1 DB5 1 DB4 0 DB3 1 DB2 0 DB1 1 DB0 0
Return to Normal Mode
This instruction returns IC into normal mode and the general commands are available. A0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
Extension Command Set 3
After entering the extension mode-3, the extension command set-3 is enabled. These commands are valid only in this mode. Always remember to return back to normal mode for correct operation.
Set Color Mode
This instruction controls the gray-scale mode. A0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 0 DB2 0 DB1 0 DB0 B/G
Flag B/G
Description B/G=0 : IC is in Gray-Scale mode (write 2-byte for 8-pixel). B/G=1 : IC is in Black/White mode (write 1-byte for 8-pixel).
Return to Normal Mode
This instruction returns IC into normal mode and the general commands are available. A0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
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10. OPERATION FLOW
10.1 Power ON Sequence
Case 1: RST=L while Power ON (Recommended) Case 2: RST=H while Power ON
Timing Requirement: Item Symbol Requirement l Recommend 0 tON-RST 50 ms l l l l VDD2 power delay tON-V2 0 tON-V2 l required. RST input time tON-RST RST=L can be input at any time after power is stable. tRW & tR should match the timing specification of RST. The recommended time just prevents abnormal display (customer can use Case 1 instead). Applying VDDI and VDDA in any order will not damage IC. If VDDI and VDDA are separated, it is recommend to turn ON VDDI first, followed by a success hardware reset, and the VDDA is the last one. Note: 1. 2. 3. 4. IC will NOT be damaged if either VDDI or VDDA is OFF while another is ON. The specification listed below just wants to prevent abnormal display on LCD module. Power stable is defined as the time that the later power (VDDI or VDDA) reaches 90% of its rated voltage. The power stable time depends on system and the time is not included in this specification (customer should consider this factor). It is recommended to keep the interface pins (A0, RWR, ERD, CSB and DB[7:0]), except RST, at "High" level before the internal reset procedure is finished. Internal VD1 generator will generate VD1 when DCPS is set to "L". The VD1 rising time is controlled by ITO resistance and the external capacitor. Before VD1 is stable, internal logic state is unstable and large current maybe occurred. This current will not damage IC. This period can be reduced by reduce the ITO resistance or the external capacitor value. Note After VDDI is stable, a successful hardware reset by RST is
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10.2 Referential Operation Flow : Initializing with internal power system
Fig. 26 Initializing with the Built-in Power Supply Circuits
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Referential Initial Code
The referential initial code is shown below. In order to be compatible with ST7541, some instructions are still included, such as the instructions with gray background). These instructions will not operate in ST7571 (just like NOP).
void Initial_ST7571(void) { Reset( ); Delay (100); Write(COMMAND, 0xAE); Write(COMMAND, 0x38); Write(COMMAND, 0xB8); Write(COMMAND, 0xA1); Write(COMMAND, 0xC8); Write(COMMAND, 0x44); Write(COMMAND, 0x00); Write(COMMAND, 0x40); Write(COMMAND, 0x00); Write(COMMAND, 0xAB); Write(COMMAND, 0x67); Write(COMMAND, 0x25); Write(COMMAND, 0x81); Write(COMMAND, 0x23); Write(COMMAND, 0x54); Write(COMMAND, 0xF3); Write(COMMAND, 0x04); Write(COMMAND, 0x93); Write(COMMAND, 0x2C); Delay (200); Write(COMMAND, 0x2E); Delay (200); Write(COMMAND, 0x2F); Delay (10); Write(COMMAND, 0xAF); }
Note: The initial code is for reference only. An optimized initial code should be checked on customer's system and LCD module.
// Delay 100ms for stable VDD1/VDD2/VDD3 // Display OFF // MODE SET // FR=1011 => 85Hz // BE[1:0]=1,0 => booster efficiency Level-3 // ADC select, ADC=1 =>reverse direction // SHL select, SHL=1 => reverse direction // Set initial COM0 register // // Set initial display line register // // OSC. ON // DC-DC step up, 8 times boosting circuit // Select regulator register(1+(Ra+Rb)) // Set Reference Voltage // EV=35 => Vop =10.556V // Set LCD Bias=1/9 V0 // Release Bias Power Save Mode // // Set FRC and PWM mode (4FRC & 15PWM) // Power Control, VC: ON // Delay 200ms // Power Control, VC: ON // Delay 200ms // Power Control, VC: ON // Delay 10ms // Display ON VR: ON VF: ON VR: ON VF: OFF VR: OFF VF: OFF
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10.3 Referential Operation Flow : Displaying Data
Fig. 27 Data Displaying Flow
10.4 Referential Operation Flow : Set Color Mode (Black/White Mode)
Gray Mode (default) Enter Test Command Set 3 Write( COMMAND, 0x7B ); Set Color Mode Write( COMMAND, 0x11 ); Exit Test Command Set 3 Write( COMMAND, 0x00 ); Black/White Mode
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10.5 Referential Operation Flow : Power-OFF
By setting 0xA9, ST7571 will go into power save mode. The LCD driving outputs are fixed to VSS, built-in power circuits are turned OFF and a discharge process starts.
Instruction Flow After the built-in power circuits are turned OFF and completely discharged, the power (VDD1 and VDD2) can be removed. Fig. 28 Power off instruction flow Note: 1. 2. 3. tPOFF: Internal Power discharge time. => 250ms (max). tV2OFF: Period between VDD1 and VDD2 OFF time. => 0 ms (min). It is NOT recommended to turn VDD1 OFF before VDD2. Without VDD1, the internal status cannot be guaranteed and internal discharge-process maybe stopped. The un-discharged power maybe flows into COM/SEG output(s) and the liquid crystal in panel maybe polarized. 4. 5. 6. 7. IC will NOT be damaged if either VDD1 or VDD2 is OFF while another is ON. The timing is dependent on panel loading and the external capacitor(s). The timing in these figures is base on the condition that: LCD Panel Size = 1.8" and C=1uF. When turning VDD2 OFF, the falling time should follow the specification: 300ms tPFall 1sec
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10.6 Referential Operation Flow : Burning EEPROM
HW Reset
Delay 120ms ( Software Coding Flow)
Initial Sequence Key Show Image 0x51
+ -
Disable Autoread 0x52 Read EE Set EE Register (for the best display quality)
Adjust Vop Offset
VE connect to VDD
VPP connect to 18V ( Software Coding Flow)
Erase EE
Write EE
Remove 18V from VPP
Remove VDD from VE
HW Reset
Delay 120ms Check Module Performance
Fig. 19 EE Burning flow chart
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Referential Software Functions void Disable_autoread(void) { Write(COMMAND, 0xD1); Write(COMMAND, 0xAA); Write(COMMAND, 0x00); } void Read_EE (void) { Write(COMMAND, 0xD1); Write(COMMAND, 0xAA); Write(COMMAND, 0x13); Write(COMMAND, 0x20); Delay(200); Write(COMMAND, 0x71); Delay(200); Write(COMMAND, 0x83); Write(COMMAND, 0x00); } void Set_EE _Register (void) { // Adjust Vop offset here // Command 0x51 and 0x52 can be set 16 times for adjusting a suitable Vop // Maxmum adjusting ranges are +/-16 levels. Write(COMMAND, 0xFD); Write(COMMAND, 0x8C); Write(COMMAND, 0x90); Write(COMMAND, 0x51); or Write(COMMAND, 0x52); Write(COMMAND, 0x00); } //0x52 for decrease Vop offset by 1 level //Enter normal mode //Enter test command set 1 //Set Vop offset highest bit Vop_j[4]=0 //Set Vop offset Vop_j[3:0]=0 //0x51 for increase Vop offset by 1 level //Enter test command set 2 //Auto-read disable //Enter EEPROM mode //Enable read mode //Delay 200ms //Set read pulse //Delay 200ms //Exit EEPROM mode //Enter normal mode //Enter test command set 2 //Disable auto-read //Enter normal mode
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void Erase_EE (void) { Write(COMMAND, 0xD1); Write(COMMAND, 0x13); Write(COMMAND, 0x4A); Delay(200); Write(COMMAND, 0x55); Delay(200); Write(COMMAND, 0x83); Write(COMMAND, 0x00); } void Write_EE (void) { Write(COMMAND, 0xD1); Write(COMMAND, 0x13); Write(COMMAND, 0x35); Delay(200); Write(COMMAND, 0x6A); Delay(200); Write(COMMAND, 0x83); Write(COMMAND, 0x00); } //Enter test command set 2 //Enter EEPROM mode //Enable write mode //Delay 200ms //Set write pulse //Delay 200ms //Exit EEPROM mode //Enter normal mode //Enter test command set 2 //Enter EEPROM mode //Enable erase mode //Delay 200ms //Set erase pulse //Delay 200ms //Exit EEPROM mode //Enter normal mode
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11. LIMITING VALUES
In accordance with the Absolute Maximum Rating System; see notes 1 and 2. Parameter Digital Power Supply Voltage Analog Power supply voltage Analog Power supply voltage LCD Power supply voltage LCD Power supply voltage Input Voltage Operating temperature Storage temperature Symbol VDD1 VDD2 VDD3 V0-XV0 VG, VM VIN TOPR TSTR Conditions -0.3 ~ 3.6 -0.3 ~ 3.6 -0.3 ~ 3.6 -0.3 ~ 15 -0.3 ~ VDD2 -0.3 ~ VDD1+0.3 -30 to +85 -40 to +125 Unit V V V V V V C C
V0
VDD
VDD VG, VM
VSS System (MPU) side
VSS
VSS
XV0 Chip side
Fig. 30 Notes 1. 2. 3. Stresses above those listed under Limiting Values may cause permanent damage to the device. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. Insure the voltage levels of V0, VDD2, VG, VM, VSS and XV0 always match the correct relation: V0 VDD2 > VG > VM > VSS XV0
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12. DC CHARACTERISTICS
Item Digital Operating Voltage Analog Operating Voltage Analog Operating Voltage High-level Input Voltage Low-level Input Voltage Input leakage current Output leakage current Symbol VDD1 VDD2 VDD3 VIHC VILC ILI ILO VIN = VDD1 or VSS VIN = VDD1 or VSS Vop=12V LCD Driver ON Resistance RON Ta =25C V=1.2V VG=2V V=0.2V VDD1~3 = 2.8V, Frame Frequency fFR 1/129 duty, N-line=0, Ta = 25C FR[3:0]=0000(77Hz) 1. VSS1 = VSS2 = VSS3 = 0 V unless otherwise specified. 70 77 84 Hz Condition Rating Min. 1.7 2.6 2.6 0.7 x VDD1 VSS -1.0 -3.0 -- -- Typ. -- -- -- -- -- -- -- 0.7 K 0.7 Max. 3.4 3.4 3.4 VDD1 0.3 x VDD1 1.0 3.0 Units V V V V V A A Applicable Pin VDD1 *2 *2 *1 *1 *3 *4 SEGn COMn *5
Bare Dice Current Consumption Using Internal Power Circuits and applying external operating voltage (VDD1, VDD2 & VDD3). Item Symbol Condition VDD1=1.8V, VDD2=VDD3=2.8V Display ON Pattern: SNOW ISS Ta = 25C, Vop=10.5V, 8X booster, 1/9 Bias, N-Line=0x01, 1/129 duty, FR[3:0]=0000(77Hz) Power Save ISS VDD1=1.8V, VDD2=VDD3=2.8V , Ta = 25C -- 5 10 A *6 -- 450 600 A *6 Rating Min. Typ. Max. Units Notes
Note: 1. 2. 3. 4. 5. The A0, D0 to D5, D6 (SI), D7 (SCL), /RD (E), /WR (R/W), CSB, IMS, OSC, P/S, /DOF, RESB, and MODE terminals. Used by internal analog circuits. The A0, /RD (E), /WR, /(R/W), CSB, IMS, OSC, P/S, /DOF, RESB and MODE terminals. Applies when the D0 to D5, D6 (SI), D7 (SCL) terminals are in a high impedance state. These are the resistance values for when a specified voltage difference is applied between the output terminals (SEGn/COMn) and the various power supply terminals (V0, XV0, VG & VM). RON = V / I 6. (V is the specified voltage difference; I is the current when applying V between output and power) It indicates the current consumed by Bare Chip alone.
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Internal Power Circuits The operation ranges of the internal power circuits are shown below: Item Vop Voltage follower output voltage VG output voltage range Internal Power Application Notes l l l l l l l Positive Booster: (VDD2 x 8 x BE) V0 or (VDD2 x 8 x BE) Vop; Negative Booster: [-VDD2 x (8 - 1) x BE] XV0 or [VDD2 x (8 - 1) x BE] (Vop - VG), where VG = Vop x 2 / N; Vop requirement: [VDD2 x (8 - 1) x BE] [Vop x (N - 2) / N] or [Vop VDD2 x (8 - 1) x BE x N / (N - 2)]. "8" is the booster stage and BE is the booster efficiency. Actual BE should be determined by module loading and ITO resistance value. 1.8V VG < VDD2. Recommend VG setting is: (VDD2-VG) = 0.5~0.8V. VM=VG/2 and 0.7V VM < VDD2. The worse condition should be considered. Furthermore, it should reserve some range for the temperature compensation and the contrast control (for end-customer). Internal Power Application Summary (Recommend LCD Module Setting) For quick reference, the following table lists some recommended settings for LCD module. VDD1=1.8V, VDD2=2.8V, N-Line=12 (0x0A), Panel Size=1.5" Duty 1/129 1/81 1/65 Note: 1. 2. It is recommended to reserve some range for user adjustment and temperature effect. The value listed above is in the IC point of view. The liquid crystal display status should be checked by customer. Vop 10V ~ 12V 9V ~ 11V 8.5V ~ 10.5V Bias 1/9 1/9 1/9 Symbol V0-XV0 VM VG Condition Rating Min. -- 0.7 1.8 Typ. -- VG/2 -- Max. 15 VDD2-0.7 VDD2 Units V V V Applicable Pin
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13. TIMING CHARACTERISTICS
System Bus Write Characteristics
8080 Series MPU
Fig. 31 (VDD1 = 1.8V~3.3V, Ta =-30~85C ) Item Address hold time Address setup time System cycle time Write L pulse width Write H pulse width WRITE Data setup time WRITE Data hold time l l l DB[7:0] /WR Signal Symbol tAH8 tAW8 tCYC8 tCCLW tCCHW tDS8 tDH8 Condition Rating Min. 0 0 500 250 250 80 30 Max. -- -- -- -- -- -- -- ns Units
A0
The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) (tCYC8 - tCCLW - tCCHW) is specified. All timing is specified using 20% and 80% of VDD1 as the reference. tCCLW is specified as the overlap between CSB being "L" and /WR being at the "L" level.
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6800 Series MPU
Fig. 32 (VDD1 = 1.8V~3.3V, Ta =-30~85C ) Item Address hold time Address setup time System cycle time Enable L pulse width (Write) Enable H pulse width (Write) WRITE Data setup time WRITE Data hold time l l l l DB[7:0] E Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tDS6 tDH6 Condition Rating Min. 0 0 500 250 250 80 30 Max. -- -- -- -- -- -- -- ns Units
A0
The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) (tCYC6 - tEWLW - tEWHW) is specified. All timing is specified using 20% and 80% of VDD1 as the reference. tEWLW is specified as the overlap between CSB being "H" and E being "L". R/W signal is always "H".
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Serial 4-Line Interface
First bit
Fig. 33
Last bit
(VDD1 = 1.8V~3.3V, Ta =-30~85C ) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time l l A0 SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 200 80 80 60 30 60 30 40 100 Max. -- -- -- -- -- -- -- -- -- ns Units
SID
CSB
The input signal rise and fall time (tr, tf) are specified at 15 ns or less. All timing is specified using 20% and 80% of VDD1 as the standard.
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Serial 3-Line Interface
Fig. 34 (VDD1 = 1.8V~3.3V, Ta =-30~85C ) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time l l SID SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Rating Min. 200 80 80 60 30 40 100 Max. -- -- -- -- -- -- -- ns Units
CSB
The input signal rise and fall time (tr, tf) are specified at 15 ns or less. All timing is specified using 20% and 80% of VDD1 as the standard.
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Serial I C Interface
2
Fig. 35 (VDD1 = 3.3V, Ta =-30~85C ) Item SCL clock frequency SCL clock low period SCL clock high period Data set-up time Data hold time SCL,SDA rise time SCL,SDA fall time Capacitive load represented by each bus line Setup time for a repeated START condition Start condition hold time Setup time for STOP condition Tolerable spike width on bus BUS free time between a STOP and START condition Note: l l All timing is specified using 20% and 80% of VDD1 as the standard. It is recommended to operate the I C interface with VDD1 higher than 2.6V.
2
Signal SCL SCL SCL SDA SDA SCL SCL
Symbol FSCLK TLOW THIGH TSU;Data THD;Data TR TF Cb
Condition
Rating Min. 1.3 0.6 100 0 20+0.1Cb 20+0.1Cb 0.6 0.6 0.6 1.3 Max. 400 0.9 300 300 400 50
Units kHZ us us ns us ns ns pF us us us ns us
SDA SDA
TSU;SUA THD;STA TSU;STO TSW
SCL
TBUF
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Reset Timing
tRW
RST
tR
Internal Status
During Reset ...
Fig. 36
Reset Finished
(VDD1 = 1.8V~3.3V, Ta =-30~85C ) Item Reset time Reset "L" pulse width RST Signal Symbol tR tRW Condition Rating Min. 120 2.0 Typ. -- -- Max. -- -- Units ms us
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14. EXTERNAL COMPONENTS
The pinning of the ST7571 is optimized for single plane wiring e.g. for chip-on-glass display modules. For VDD1 = 3.0V ~ 3.3V For VDD1 = 1.8V ~ 2.8V
Fig. 37 Note: 1. 2.
External Components
The resistors are reserved only. Please reserve the space for them on FPC (or system). The capacitors in these 2 cases are not same. C4 is not used if VDD1 is 1.8V ~ 2.8V.
Recommend Value: (for typical 1.6" LCD panel) l l C1~C3: 1uF ~ 4.7uF C4: 0.1uF ~ 1uF
Components selection notes: l l l l l Higher capacitor values are recommended for ripple reduction. In order to avoid the characteristic differences of the LCD panel. The capacitor values should be verified according to the display performance on LCD panel. If the display panel is larger (> 2"), higher capacitor (C1~C3) values are recommended. If the display panel is smaller (< 1"), lower capacitor (C1~C3) values can be used. The resistor is reserved for discharge in the worse case, when VDD suddenly drops to 0.
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15. APPLICATION PROGRAM EXAMPLE
Programming example for displaying data with ST7571: Step A0 1 0 0 2 3.a A0 0 A0 0 A0 3.b 0 0 3.c A0 0 A0 0 A0 0 A0 5 1 1 A0 6 1 1 A0 7 1 1 A0 8 1 1 A0 9 1 1 A0 10 1 1 0 0 1 0 1 x' 0 0 0 0 0 0 x' 1 1 0 1 1 0 Bus Status DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 1 1 1 0 0 0 0 0 R2 0 0 x' 1 R1 0 0 0 1 R0 1 LCD Display Operation Description Mode Set: FR[3:0]=0000; BE[1:0]=10 OSC ON Set Ra/Rb (R[2:0])
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Set contrast (EV[5:0])
EV5 EV4 EV3 EV2 EV1 EV0 0 1 0 B2 B1 B0 Set Bias (B[2:0]) Set Power Control
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
4.a
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 1 1
Booster=ON, Regulator=ON, Follower=ON Display Control Display ON Write Data X, Y are default 0 after reset. Skip setting X & Y here.
4.b
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 1 0 1 1 1 1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 Write Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 Write Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 Write Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 Write Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write Data
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Step A0 11 1 1 A0 12 1 1 A0 13 1 1 Bus Status DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 Write Data LCD Display Operation Description
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Write Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 Display Control: Set Reverse display mode (REV=1) Set Column Address Set address to "00000000" X[7:0]=0x00 (X0 default is 0) Write Data
14
A0 0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 1 0 0 1 1 1
A0 15 0 0 A0 16 1 1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write Data
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Programming example for displaying data with ST7571 (for I C Interface): Step 1 2 3 I C Interface Start DB7 DB7 0 DB7 4 0 0 5 6.a DB7 1 DB7 0 DB7 6.b 1 x' 6.c DB7 0 DB7 0 DB7 1
2 2 2
Bus Status
LCD Display
Operation Description
DB6 DB6 0 DB6 0 0 DB6 0 DB6 0 DB6 0 x' DB6 1 DB6 0 DB6 0
DB5 DB5 0 DB5 1 0 DB5 1 DB5 1 DB5 0 EV5 DB5 0 DB5 1 DB5 1
DB4 DB4 0 DB4 1 0 DB4 0 DB4 0 DB4 0 EV4 DB4 1 DB4 0 DB4 0
DB3 DB3 0 DB3 1 1 DB3 1 DB3 0 DB3 0 EV3 DB3 0 DB3 1 DB3 1
DB2 DB2 0 DB2 0 0 DB2 0 DB2 R2 DB2 0 EV2 DB2 B2 DB2 1 DB2 1
DB1 DB1 0 DB1 0 x' DB1 1 DB1 R1 DB1 0 EV1 DB1 B1 DB1 1 DB1 1
DB0 DB0 0 DB0 0 0 DB0 1 DB0 R0 DB0 1 EV0 DB0 B0 DB0 1 DB0 1
Slave address for write Set Control Byte Co=0; A0=0 Mode Set: FR[3:0]=0000; BE[1:0]=10 OSC ON Set Ra/Rb (R[2:0])
Set contrast (EV[5:0])
Set Bias (B[2:0]) Set Power Control
7.a
Booster=ON, Regulator=ON, Follower=ON Display Control Display ON Re-start
7.b 8 9 10
I C Interface Start DB7 DB7 0 DB7 DB6 DB6 1 DB6 0 0 DB6 1 1 DB6 1 1 DB6 1 1 DB5 DB5 0 DB5 1 1 DB5 0 0 DB5 0 0 DB5 0 0 DB4 DB4 0 DB4 0 0 DB4 0 0 DB4 0 0 DB4 0 0 DB3 DB3 0 DB3 0 0 DB3 1 1 DB3 1 1 DB3 1 1 DB2 DB2 0 DB2 1 1 DB2 0 0 DB2 0 0 DB2 0 0 DB1 DB1 0 DB1 1 1 DB1 0 0 DB1 0 0 DB1 0 0 DB0 DB0 0 DB0 0 0 DB0 1 1 DB0 1 1 DB0 1 1 68/76
Slave address for write Set Control Byte Co=0; A0=1 Write Data X, Y are default 0 after reset. Skip setting X & Y here.
11
0 0 DB7
12
0 0 DB7
Write Data
13
0 0 DB7
Write Data
14
0 0
Write Data
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ST7571
Step DB7 15 0 0 DB7 16 0 0 DB7 17 0 0 DB7 18 0 0 DB7 19 0 0 20 21 22
2
Bus Status DB6 0 0 DB6 0 0 DB6 1 1 DB6 1 1 DB6 1 1 DB5 1 1 DB5 0 0 DB5 0 0 DB5 1 1 DB5 0 0 DB4 1 1 DB4 0 0 DB4 0 0 DB4 1 1 DB4 0 0 DB3 0 0 DB3 0 0 DB3 0 0 DB3 1 1 DB3 0 0 DB2 0 0 DB2 0 0 DB2 0 0 DB2 1 1 DB2 0 0 DB1 1 1 DB1 0 0 DB1 0 0 DB1 1 1 DB1 0 0 DB0 0 0 DB0 0 0 DB0 1 1 DB0 1 1 DB0 1 1
LCD Display
Operation Description
Write Data
Write Data
Write Data
Write Data
Write Data
I C Interface Start DB7 DB7 1 DB7 1 DB7 1 DB7 DB6 DB6 0 DB6 0 DB6 0 DB6 0 0 DB6 1 DB6 0 0 DB5 DB5 0 DB5 1 DB5 0 DB5 0 0 DB5 0 DB5 0 0 DB4 DB4 0 DB4 0 DB4 0 DB4 1 0 DB4 0 DB4 0 0 DB3 DB3 0 DB3 0 DB3 0 DB3 0 0 DB3 0 DB3 0 0 DB2 DB2 0 DB2 1 DB2 0 DB2 0 0 DB2 0 DB2 0 0 DB1 DB1 0 DB1 1 DB1 0 DB1 0 0 DB1 0 DB1 0 0 DB0 DB0 0 DB0 1 DB0 0 DB0 0 0 DB0 0 DB0 0 0
Re-start Slave address for write Set Control Byte Co=1; A0=0 Display Control: Set Reverse display mode (REV=1) Set Control Byte Co=1; A0=0 Set Column Address Set address to "00000000" X[7:0]=0x00 (X0 default is 0) Set Control Byte Co=1; A0=1
23
24
25
0 0
26
DB7 1 DB7
27
0 0
Write Data
28
I C Interface Stop
2
STOP I C transmission
2
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16. APPLICATION NOTES
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ST7571 Specification Revision History
Version 1.0 Date 2008/01/29 1. 1. 2. 1.1 2008/04/02 3. 4. 5. 1. 2. 3. 1.2 2008/08/08 4. 5. 6. 7. 1.3 2008/12/19 1. 2. 1. 2. 3. 4. 1.4 2009/03/13 5. 6. 7. 8. 9. 1.4a 2009/03/16 1. 2. 1. 2. 3. 4. 5. 6. 1.4b 2009/05/13 7. 8. 9. Official Release. Remove CSL=L setting. Modify Application note Add Initial code Modify ITO layout reference Modify 9.1.14 entire display Re-arrange sections for document format issue. Remove one of the Power OFF flow (not easy control by customer). Update recommend N-Line setting as 12-line (0x0A). Rewrite some description for easy understanding and grammar issue. Fix wrong Limiting Values. Rewrite DC Characteristics section. Separate Internal Power Application Note for detailed description. Modify Recommend LCD Vop Setting: use same bias for easy use. Modify limiting voltage values. Modify 8080/6800 system cycle time. Remove reversion history before Ver. 1.0. Redraw broken figures. Rewrite Section 7.5 RESET CIRCUITS for easy understanding. Rewrite descriptions for easy understanding. Update Power ON Sequence information. Add 0x8C & 0x90 to "Set_EE_Register" at Software Function Program. Fix COM pad naming in figures. Update external components information. Match the instruction name with the instruction description. Modify drawing: RST waveform at 10.1 Power ON Sequence Section (Case 2). Fix typing mistakes. Redraw IC outline (Page 2) and use only one view direction for IC and PAD. Fix typing mistakes and rewrite descriptions for easy understanding. Add ITO limitation of I C interface signal SDA (Page 14). Fix naming issue on Page 17, 22, 35. Column Address should be X[7:0] (not Y[7:0]). The default value of FR[3:0] after reset is missing in previous version. Rearrange the operation flow information into one section: "Section 10. OPERATION FLOW" (Page 48). Rename section "10. COMMAND DESCRIPTION" to be "10. OPERATION FLOW." Add note of I C: "VDD1 higher than 2.6V". Add notes to Section 14. EXTERNAL COMPONENTS. Modify the value to be a range.
2 2
Description
10. Fix Section 15. APPLICATION PROGRAM EXAMPLE mistakes. 11. Update detailed settings into Section 16. APPLICATION NOTES: Different circuit for different VDD1 level (C4 is not used if VDD1 is 1.8V or 2.8V). Reserve 2 more resistors.
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ST7571 Specification Revision History
1. 2. 3. 1.5 2009/6/25 4. 5. 6. 7. 1.5a 2009/7/21 1. Fix typing mistakes. Add axis into Section 3. PAD ARRANGEMENT (COG). Modify referential codes: use 8-bit format, keep delay time same as description. Mark no operation instructions in initial code (Page 50). Add Test Instructions into instruction table. Reserve external components for special case. Define the VDD2 voltage range: 2.7V ~ 3.3V (cover 2.6V ~ 3.4V). Add description of Extension Command Sets.
Ver 1.5a
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